The electronics industry continues to rely upon advances in semiconductor technology to realize higher-functioning devices in more compact areas. For many applications, realizing higher-functioning devices requires integrating a large number of electronic devices onto a single silicon wafer. As the number of electronic devices per given area of the silicon wafer increases, the manufacturing process becomes more difficult.
A large variety of semiconductor devices has been manufactured having various applications in numerous disciplines. Such silicon-based semiconductor devices often include metal-oxide-semiconductor MOS) transistors, such as P-channel MOS (PMOS), N-channel MOS (NMOS) and complementary MOS (CMOS) transistors, bipolar transistors, BiCMOS transistors.
Each of these semiconductor devices generally includes a semiconductor substrate on which a number of active-devices are formed. The particular structure of a given active device can vary between device types. For example, in a MOS transistor, an active device generally includes a source and drain region and a gate electrode. The gate modulates current between the source and drain regions.
One important step in the manufacturing of such semiconductor devices is the formation of active devices, or portions thereof, using photolithography and etching processes. In photolithography, a wafer substrate is coated with a light-sensitive material called photo-resist. Next, the wafer is exposed to light; the light striking the wafer is passed through a mask plate. This mask plate defines the desired features to be printed on the substrate. After exposure, the resist-coated wafer substrate is developed. The desired features as defined on the mask are retained on the photoresist-coated substrate. Unexposed areas of resist are washed away with a developer. The wafer having the desired features defined is subjected to etching. Depending upon the production process, the etching may either be a wet etch, in which liquid chemicals are used to remove wafer material or a dry etch, in which wafer material is subjected to a radio frequency (RF) induced plasma. The features required on an integrated circuit are built with a number of thin films. The reliable formation of thin films with the desirable characteristics of resistivity , adhesion, and topology presents a challenge. One group of thin films is refractory silicides, needed as the process scales downward into the sub-micron realm
As minimum geometries decrease, interconnect resistances increase. For technologies with minimum geometries of about half a micron, introducing a refractory metal polycide process significantly lowers gate interconnect resistance. In minimum geometry features, tungsten silicide and molybdenum silicides are the materials of choice for their low sheet resistances and thermal stability. The development of Self-Aligned silicide (SALICIDE) technology has allowed further reductions in minimum geometries with increased performance specifications. With salicide technology, not only is the gate interconnect resistance reduced, source-drain interconnect and external transistor resistances are reduced as well because all exposed silicon regions are silicided at the same time. This provides substantial circuit performance increases. While there has been some work on other silicides, much of the development of high performance CMOS circuits centers on titanium silicide. Tungsten is often chosen for its low resistivity. Tungsten can be silicided at temperatures normally found in semiconductor processing because its thermal stability is compatible with semiconductor processing. Etches that are selective to tungsten's silicides are known in the art.
Silicide films are used to provide low resistance interconnection paths which are important in order to fabricate dense, high performance devices. One structure is a polycide gate of the MOS transistor. It consists of a refractory metal silicide (e.g., WSi2, TiSi2, MoSi2, or TaSi2) on top of a doped poly-silicon layer. In an example process, such a structure reduces the interconnect resistivity to less than the 15-30 ohms/square exhibited by doped poly-silicon that has no silicide. One commonly used silicide is tungsten silicide, WSi2.
Reactive Ion Etching (RIE) is often used to selectively etch a substrate on which the desired features of the integrated circuit have been defined through photolithography. The etching begins by introducing a process gas into a chamber. A plasma is ignited in the chamber to create an etch gas from the process gas. The etch gas etches the substrate to create volatile etch byproduct compounds. These compounds are then removed from the chamber. RIE is sometimes used to etch tungsten silicide.
An example prior art recipe for RIE etching WSi2 is a mixture of SF6, HBr, and an inert gas such as He. A significant shortcoming of this recipe is that it may make it difficult to attain vertical sidewall profiles that approach 90°. Ideally, the 90° profile is obtained when the process gas anisotropically etches the substrate and etching proceeds vertically through the uncoated portions of the substrate. A typical sidewall profile angle θ is about 75°. It is desirable to achieve a sidewall profile angle of more than 80° and preferably, in the range of about 85° to 90°.
The etch chemistry should not undercut features below the resist layer, as this often results in “reentrant” in sidewall profiles that form angles less 85° with the substrate. Reentrant profiles are caused by isotropic etching or undercutting, which occurs when etching proceeds horizontally below the resist layer, instead of vertically through the uncoated portions. Such reentrant profiles can sometimes be created as a result of RIE etching.
RIE systems may cause high profile “microloading.” High profile microloading occurs when the cross-sectional profiles of the features vary as a function of the spacing between them. Advantageous etching processes provide features with uniform cross-sections regardless of the distance between the features or their density.
It is also advantageous to obtain high etch rates and high etching selectivity ratios for process efficiency. A high selectivity ratio is desirable to avoid excessive etching of the resist layer that can result in etching of the substrate below the resist layer. The etch selectivity ratio is the ratio of the WSi2 etch rate to the resist etch rate. The selectivity ratio of tungsten silicide to the underlying doped poly-silicon layer is ideally one to one. This targeted ratio minimizes the effect of the non-uniformity of the tungsten silicide etch process, which for some process parameters can be large.
Accordingly, there is a need for a process to selectively etch tungsten silicide on semiconductor substrates that provides substantial anisotropic etching and reduced profile micro-loading. It is also desirable to obtain high etch rates and a high substrate-to resist-etch selectivity ratio. In addition, process non-uniformity should be low or the selectivity to poly-silicon should approach one to one.